With increasing demands on functionality and performance as well as improved fabrication techniques, newer generations of processors and other integrated circuits have significantly higher levels of integration than their predecessors. Additionally, in some instances, different market segments may exist for compatible versions of processors and other types of integrated circuits having price and performance characteristics specific to a particular market segment. However, given the complexity and expense of designing a single version of a processor or other integrated circuit having a large transistor count, it may be impractical to separately design and manufacture a processor for each of several different market segments.
These issues may be compounded as mobile devices become more pervasive. Specifically, mobile systems typically suffer from power leakage and consumption of their internal circuits. Currently, low-power circuits are based on conventional design schemes. Moreover, mobile multi-core processor and multi-chip systems require a fundamentally different design approach for cores and on-chip memories. Under such configurations, multiple chipsets may be utilized in a single system, with each chipset requiring separate memory resources. Such scattered memory resources may lead to extensive power leakage.
Heretofore, attempts have been made in providing improved circuitry. Such attempts include the following:
U.S. Patent Application Publication No. US 2008/0244222 discloses a method for virtual processing.
U.S. Patent Application Publication No. US 2005/0114586 discloses a method of performing memory mapped input/output operations to an alternate address space.
U.S. Pat. No. 7,984,122 discloses an approach in which processor core data regarding a client device is received from the client device.
U.S. Pat. No. 7,873,776 discloses a multiple-core processor with support for multiple processors.
U.S. Pat. No. 7,849,327 discloses a technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment.
U.S. Pat. No. 7,552,436 discloses a method of performing memory mapped input/output operations to an alternate address space.
Unfortunately, none of these approaches addresses issues such as power leakage and/or consumption for multiple chipset designs.